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HDL Coder Workflow

FPGAs can be used to acquire and generate high-frequency signals, simulate plants, and run controls and signal processing algorithms using HDL Coder from MathWorks.

Common applications include:

  • Closed-loop rates of 20 kHz to 1 MHz, e.g. for motor control and simulation, power conversion, and battery systems
  • Pre-processing of high-speed analog signals, e.g. by applying filters, or to store large amounts of data, and use average or sample values for closed-loop controls only
  • Pre-processing of vision data, e.g. to analyze and store data, and then provide input for the closed loop if required
  • Final embedded target uses FPGAs or ASICs: prototyping on FPGAs therefore simplifies migration to the embedded platform

Running Simulink® designs on Speedgoat Simulink-programmable FPGA I/O modules using HDL Coder reduces development times and enables you to simulate and verify your algorithm early in the process. This workflow also reduces the number of development cycles on the hardware itself:

  • Automatically generate HDL code and synthesize your floating-point or fixed-point Simulink model
  • Automatically build and download your real-time application to the FPGA I/O module installed in a Speedgoat target machine
  • Run the application in real-time with the click of a button, log data, and monitor and tune parameters

Note that for some Simulink blocks, floating and fixed-point support restrictions may apply. Floating-point support with HDL Coder is ideal for algorithms such as IIR filters, tangents, divisions, and any feedback loops that are difficult to converge. Fixed-point implementations are often more suitable for algorithms such as FIR filters, FFTs, and NCO/mixers.

Hardware requierements

Software requirements

For more information about software and hardware prerequisites, refer to the software installation and configuration guide.


Speedgoat FPGA I/O modules and Simulink Real-Time™, together with Simulink Coder™ for C, and HDL Coder™ for HDL code generation make it easy to leverage all the benefits of FPGA technology:

Task With Simulink Coder only With HDL Coder
Acquire and generate high-frequency analog and digital signals up to 10 Gsps
Achieve closed-loop sample rates up to 20-100kHz depending on model complexity and I/O channel count
Achieve closed-loop rates above 20-100kHz, depending on model complexity and I/O channel count  
Pre-process or replay signal data on FPGAs  
Leverage FPGA code modules with FPGA I/O modules
Run floating and fixed point implementations
(some restrictions with HDL Coder may apply depending on your application and the MATLAB release used)
Integrate custom HDL code into Simulink design  
Log data to x86 RAM, SSD, or to external RAM of the FPGA I/O module
Run algorithms designed with Simulink on multiple CPU cores and multiple synchronized target machines, at multiple synchronized sample rates  
Run algorithms designed with Simulink on multiple CPU cores and CPUs, and multiple FPGAs, interconnected with low-latency links, at multiple synchronized sample rates
Monitor parameters and tune application during real-time execution


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